SPI Registers in AVR

Most controllers in the AVR family support SPI. AVR has 3 register associated with the SPI.

1.       SPSR (SPI Status Register)

2.       SPCR (SPI Control Register)

3.       SPDR (SPI Data Register)

Serial Peripheral Interface Protocol

SPI – Serial Peripheral Interface is a bus interface used in many peripheral devices and nowadays almost all microcontrollers have it. Basically it connects a single masters to multiple slaves. So a single master controller can receive and transmit data to multiple slave microcontrollers.

General Purpose DMA (GPDMA)

DMA Controller

 The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bi-directional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral.

General Purpose DMA Controller

The General Purpose Direct Memory Access Controller (GPDMA) can transfer blocks of data between memory mapped locations. It can do this in parallel to the CPU code execution, and also in parallel to Ethernet DMA operations on the second AHB bus.
 
There are two channels in the GPDMA. You can think of them as two block transfer tasks, which can be activated at the same time. Both channels offer equivalent functionality.

The following transfer types are supported by each channel:

• Memory-to-Memory transfers
• Memory-to-Peripheral transfers
• Peripheral-to-Memory transfers
• Peripheral-to-Peripheral transfers

As the GPDMA is located at AHB1 bus, its scope is everything an AHB1 master can access. This includes the AHB1 RAM block starting at address 0x7FD00000, all external memory via the EMC, and of course the APB peripherals through the AHB1-APB bridge. Memory on the AHB2 bus (the Ethernet segment) and the CPU’s local bus memory (flash and system SRAM) are not accessible by the GPDMA.

Not all APB peripherals are DMA ready, but a selection of them:

• SSP0 (Synchronous Serial Interface)
• SSP1 (Synchronous Serial Interface)
• I2S (Audio Interface)
• MCI (SD Card/MMC Memory Card Interface) 

The LPC17xx has these DMA Features

 • Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported.
• GPDMA supports the SSP, I2S, UART, A/D Converter, and D/A Converter peripherals. DMA can also be triggered by a timer match condition. Memory-to-memory transfers and transfers to or from GPIO are also supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface.
• One AHB bus master for transferring data. The interface transfers data when a DMA request goes active.
• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking.
• DMA can operate in Sleep mode. (Note that in Sleep mode the GPDMA cannot access the Flash memory).

Brownout Protection

Well almost all microcontrollers have Brownout protection inbuilt in them but when connecting a controller to an industry sensor and controlling devices(which are extremely costly) its better we know what is a brownout and how is it detected in a microcontroller cause many devices in low to medium scale industry may not be as immune to brownout as our controller.

So whats a brown out??

Wikipedia defines Brownout as an intentional or unintentional drop in voltage in an electrical power supply system. Intentional brownouts are used for load reduction in an emergency. The reduction lasts for minutes or hours, as opposed to short-term voltage sag or dip.

The brown out can cause one of the three things for a dc supply system. These things in turn can damage the connected embedded systems.

1. An unregulated direct current supply will produce a lower output voltage for electronic circuits. The output ripple voltage will decrease in line with the usually reduced load current.
2. A linear direct current regulated supply will maintain the output voltage unless the brownout is severe and the input voltage drops below the drop out voltage for the regulator, at which point the output voltage will fall and high levels of ripple from the rectifier/reservoir capacitor will appear on the output.
3. A switched-mode power supply which has a regulated output will be affected. As the input voltage falls, the current draw will increase to maintain the same output voltage and current, until such a point that the power supply malfunctions.

Brownouts can cause unexpected behaviour in systems with digital control circuits. Reduced voltages can bring control signals below the threshold at which logic circuits can reliably detect which state is being represented. As the voltage returns to normal levels the logic can latch at an incorrect state; even can't happen states become possible. The seriousness of this effect and whether steps need to be taken by the designer to prevent it depends on the nature of the equipment being controlled; for instance a brownout may cause a motor to begin running backwards.

Nested Vectored Interrupt Controller (NVIC)

What is NVIC?

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

Interrupt latency is the time that elapses from when an interrupt is generated to when the source of the interrupt is serviced.

The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require any assembler stubs, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another.

Tail-chaining is back-to-back processing of exceptions without the overhead of state saving and restoration between interrupts. The processor skips the pop of eight registers and push of eight registers when exiting one ISR and entering another because this has no effect on the stack contents.

The processor tail-chains if a pending interrupt has higher priority than all stacked exceptions. For more info on Tail Chaining and its Timing Diagram Refer infocentre@arm.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down.

Features

1. Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3
2. Tightly coupled interrupt controller provides low interrupt latency
3. Controls system exceptions and peripheral interrupts
4. In the LPC17xx, the NVIC supports 35 vectored interrupts
5. 32 programmable interrupt priority levels, with hardware priority level masking
6. Relocatable vector table
7. Non-Maskable Interrupt
8. Software interrupt generation

Cortex M3 Processor

The ARM Cortex™-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applications, specifically developed to enable developers to develop high-performance low-cost platforms for a broad range of devices including microcontrollers, automotive body systems, industrial control systems and wireless networking and sensors. The processor delivers outstanding computational performance and exceptional system response to events while meeting the challenges of low dynamic and static power constraints. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area.

Why Cortex-M3??

Delivering higher performance and richer features

Introduced in 2004 and recently updated with new technologies and configurability, the Cortex-M3 is the mainstream ARM processor developed specifically with microcontroller applications in mind.

Performance and Energy Efficiency 

With high performance and low dynamic power consumption the Cortex-M3 processor delivers leading power efficiency. Coupled with integrated sleep modes and optional state retention capabilities the Cortex-M3 processor ensures there is no compromise for applications requiring low power and excellent performance.

Full featured

The processor executes Thumb^®-2 instruction set for optimal performance and code size, including hardware division, single cycle multiply, and bit-field manipulation. The Cortex-M3 NVIC is highly configurable at design time to deliver up to 240 system interrupts with individual priorities, dynamic reprioritization and integrated system clock.

Rich connectivity

The combination of features and performance enables Cortex-M3 based devices efficiently to handle multiple I/O channels and protocol standards such as USB OTG (On-The-Go). 

Energy efficiency advantage

The demand for ever lower-cost products with increasing connectivity (e.g. USB, Bluetooth, IEEE 802.15) and sophisticated analog sensors (e.g. accelerometers, touch screens) has resulted in the need to more tightly integrate analog devices with digital functionality to pre-process and communicate data. Most 8-bit devices do not offer the performance to sustain these tasks without significant increases in MHz and therefore power, and so embedded developers are required to look for alternative devices with more advanced processor technology. The 16-bit devices have previously been used to address energy efficiency concerns in microcontroller applications. However, the relative performance inefficiencies of 16-bit devices mean they will generally require a longer active duty cycle or higher clock frequency to accomplish the same task as a 32-bit device.

Ease of software development

Software development for ARM Cortex processor-based microcontrollers can be much easier than for 8-bit microcontroller products. Not only is the Cortex processor fully C programmable, it also comes with various enhanced debug features to help locating problems in software. There are also plenty of examples and tutorials on the internet, including many from ARM processor-based MCU vendor's websites, alongside any additional resources included in MCU development kits.

Cortex M3 Processor Simplified Block Diagram

Cortex M3 Processor Block Diagram. Ref ARM.com

 Cortex M3 Core Peripherals

• Nested Vectored Interrupt Controller
  The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing.
• System control block
  The System control block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions.
• System timer
  The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter.
• Memory protection unit
  The Memory protection unit (MPU) improves system reliability by defining the memory attributes for different memory regions. It provides up to eight different regions, and an optional predefined background region.

Moving to Cortex M3

Programming an 8 bit microcontroller was fun. But now i am moving to big boys 32 bit industry standard microcontrollers. So i have started with cortex m3 nxp's LPC1768 microcontroller. So first few posts i will start with its basic features and their theory in short. I will try to compile all important features in posts and then will start posting examples.

My open source project for same. [Cortex M3 Applications]
My board(Landtiger) Details. [Source Forge Link][Landtiger Feature Video]

Updates are under progress. So gotta wait till all pages/topics are fully prepared and updated.