Nested Vectored Interrupt Controller (NVIC)

What is NVIC?

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

Interrupt latency is the time that elapses from when an interrupt is generated to when the source of the interrupt is serviced.

The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require any assembler stubs, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another.

Tail-chaining is back-to-back processing of exceptions without the overhead of state saving and restoration between interrupts. The processor skips the pop of eight registers and push of eight registers when exiting one ISR and entering another because this has no effect on the stack contents.

The processor tail-chains if a pending interrupt has higher priority than all stacked exceptions. For more info on Tail Chaining and its Timing Diagram Refer infocentre@arm.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down.

Features

1. Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3
2. Tightly coupled interrupt controller provides low interrupt latency
3. Controls system exceptions and peripheral interrupts
4. In the LPC17xx, the NVIC supports 35 vectored interrupts
5. 32 programmable interrupt priority levels, with hardware priority level masking
6. Relocatable vector table
7. Non-Maskable Interrupt
8. Software interrupt generation