General Purpose DMA (GPDMA)

DMA Controller

 The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bi-directional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral.

General Purpose DMA Controller

The General Purpose Direct Memory Access Controller (GPDMA) can transfer blocks of data between memory mapped locations. It can do this in parallel to the CPU code execution, and also in parallel to Ethernet DMA operations on the second AHB bus.
 
There are two channels in the GPDMA. You can think of them as two block transfer tasks, which can be activated at the same time. Both channels offer equivalent functionality.

The following transfer types are supported by each channel:

• Memory-to-Memory transfers
• Memory-to-Peripheral transfers
• Peripheral-to-Memory transfers
• Peripheral-to-Peripheral transfers

As the GPDMA is located at AHB1 bus, its scope is everything an AHB1 master can access. This includes the AHB1 RAM block starting at address 0x7FD00000, all external memory via the EMC, and of course the APB peripherals through the AHB1-APB bridge. Memory on the AHB2 bus (the Ethernet segment) and the CPU’s local bus memory (flash and system SRAM) are not accessible by the GPDMA.

Not all APB peripherals are DMA ready, but a selection of them:

• SSP0 (Synchronous Serial Interface)
• SSP1 (Synchronous Serial Interface)
• I2S (Audio Interface)
• MCI (SD Card/MMC Memory Card Interface) 

The LPC17xx has these DMA Features

 • Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported.
• GPDMA supports the SSP, I2S, UART, A/D Converter, and D/A Converter peripherals. DMA can also be triggered by a timer match condition. Memory-to-memory transfers and transfers to or from GPIO are also supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface.
• One AHB bus master for transferring data. The interface transfers data when a DMA request goes active.
• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking.
• DMA can operate in Sleep mode. (Note that in Sleep mode the GPDMA cannot access the Flash memory).