Most controllers in the AVR
family support SPI. AVR has 3 register associated with the SPI.
1. SPSR
(SPI Status Register)
2. SPCR
(SPI Control Register)
3. SPDR
(SPI Data Register)
SPSR (SPI Status Register)
SPIF
|
WCOL
|
-
|
-
|
-
|
-
|
-
|
SPI2X
|
SPIF
|
SPI Interrupt flag bit.
|
In master mode this bit is set
in 2 situations
1. When
a serial transfer is completed
2. When
SS pin is an input and is driven low by an external device
Setting SPI Interrupt Flag to
1 will cause an interrupt, if SPI Interrupt is enabled in SPI Control
Register and the global interrupts are also enabled.
|
|
WCOL
|
Write Collision Flag bit.
|
This bit is set if one writes
on SPI Data Register during a data transfer
|
|
SPI2X
|
SPI Double Speed bit.
|
When SPI is in master mode setting this bit to 1 doubles the SPI
Speed
|
Both WCOL and SPIF bit are
cleared when we read the SPI status register and then access the SPI Data
Register. Alternatively the SPIF bit is cleared by hardware when executing the
corresponding interrupt handler.
SPCR (SPI Control Register)
SPIE
|
SPE
|
DORD
|
MSTR
|
CPOL
|
CPHA
|
SPR1
|
SPR0
|
SPIE
|
SPI Interrupt Enable bit
|
Setting this bit to one
enables the SPI interrupt.
|
|
SPE
|
SPI Enable bit
|
Setting this bit to one
enables the SPI.
|
|
DORD
|
Data Order bit
|
This bit decided the order of
transfer
DORD – 1 LSB is transmitted
first.
DORD – 0 MSV is transmitted
first.
|
|
MSTR
|
Master/Slave Select bit
|
This bit decides whether the
device will act as master or a slave.
MSTR = 1 Master Mode Selected
MSTR = 0 Slave mode is
selected
|
|
CPOL
|
Clock Polarity
|
This bit sets the base value of clock when it is idle.
CPOL = 0 the base value of clock is 0
CPOL = 1 the base value of clock is 1.
|
|
CPHA
|
Clock Phase
|
Determines on which edge it should sample. Leading or trialing.
CPHA = 0 means sample on the leading edge
CPHA = 1 means sample on the trailing edge.
|
|
SPR1,SPR0
|
SPI clock rate select 1 and 0
|
These two bits along with the
SPI2X bit determine the SCK rate of the device in the master mode.
|
The table below shows the SCK frequency for various select
options.
SPI2X
|
SPR1
|
SPR0
|
SCK Frequency
|
0
|
0
|
0
|
Fosc/4
|
0
|
0
|
1
|
Fosc/16
|
0
|
1
|
0
|
Fosc/64
|
0
|
1
|
1
|
Fosc/128
|
1
|
0
|
0
|
Fosc/2
|
1
|
0
|
1
|
Fosc/16
|
1
|
1
|
0
|
Fosc/32
|
1
|
1
|
1
|
Fosc/64
|
SPDR SPI Data Register
This is a read/write register.
To write into the SPI shift register data must be written in the SPI data
register. Similaryl to read from the Shift Register the data must be read from
the SPDR register. Writing to SPDR initiates the data transmission.
One cannot write data to SPDR
until the last of the bit is completely transmitted. Otherwise a collision will
happen. One can read the received data before another byte of the data is
received completely.
Slave Select (SS) pin AVR
Master mode
|
In this user has the control to make Slave Select (SS) pin an input
or an output pin
|
SS as Output Pin = SPI circuit of AVR will not control the SS
pin. We can make it 1 or 0 by software.
SS as Input Pin = SPI circuit of AVR will control the function of
SS pin. User will not be able to change it in the software. In this case we
need to externally make SS pin high to ensure the master operation. If an
external device makes the SS pin low, the SPI module stops working in master
mode and switches to slave mode by clearing the MSTR bit in the SPCR, and
then sets the SPIF bit in the SPSR.
It’s a recommended practice to
use SS pin as output when we do not want to be interrupted in the master mode
operation of the device.
|
|
Slave Mode
|
In this the SS pin is always input. User has no control over its
direction.
|
In slave mode SS pin is always
input and we cannot control it by the software. We need to hold it externally
low to activate the SPI. When SS is driven high, SPI is disabled and all pins
of SPI become inputs.
When we are working in slave
mode and the SS pin is driven high by an external device, the SPI module is
reset but not disabled and it is necessary to enable it again.
|
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