Instruction Set - Preference of C over Assembly

Well we all know what instruction set is. An instruction set is a group of instructions a machine “understands“ to execute. So cutting to the chase, ATmega 16 has 131 different instruction. For the most efficient and fast execution of a given microcontroller, assembly language should be used. Assembly language is written to efficiently interact with a specific microcontroller’s resident hardware. One needs to learn assembly language instruction specific to the device to be effecient with programming the device in a assembly language program. But the only problem the program is not transferrable to other devices.

So we program in C, to increase the portability of program to similar architectural devices. Like to a whole AVR line devices we can use the same program written for ATmega16. When a C program is compiled during the software development process, the program is first converted to assembly language and then to the machine code for the specific microcontroller. We must emphasize that programming in C is not better than assembly language or vice versa. Both approaches have their inherent advantages and disadvantages. That we all know of.(assuming).

RISC – Reduced Instruction Set Computer

Microcontroller is described as an entire computer system contained within a single integrated circuit or chip. Microcontroller operation is controlled by a user written program interacting with the fixed hardware architecture resident within the microcontroller. A specific microcontroller architecture can be categorized as accumulator-based, register-based, stack-based, or a pipeline architecture.

Consider Atmel’s ATmega16. Its a register-based architecture. In this type of architecture, both operands of an operation are stored in registers collocated with the central processing unit (CPU). This means that before an operation is performed, the computer loads all necessary data for the operation to its CPU. The result of the operation is also stored in a register. During program execution, the CPU interacts with the register set and minimizes slower memory accesses. Memory accesses are typically handled as background operations. Coupled with the register-based architecture is an instruction set based on the

RISC concept. A RISC processor is equipped with a complement of very simple and efficient basic operations. More complex instructions are built up from these very basic operations. This allows for efficient program operation. The Atmel ATmega16 is equipped with 131 RISC-type instructions. Most can be executed in a single clock cycle. The ATmega16 is also equipped with additional hardware to allow for the multiplication operation in two clock cycles. In many other microcontroller architectures, multiplication typically requires many more clock cycles.

The Atmel ATmega16  is equipped with 32 general purpose 8-bit registers that are tightly coupled to the processor’s arithmetic logic unit within the CPU. Also, the processor is designed following the Harvard Architecture format. That is, it is equipped with separate, dedicated memories and buses for program and data information. The register-based Harvard Architecture coupled with the RISC-based instruction set allows for fast and efficient program execution and allows the processor to complete an assembly language instruction every clock cycle. Atmel indicates the ATmega16 can execute 16 million instructions per second when operating at a clock speed of 16 MHz.

8086 Memory Banks

The 8086 has 20-bit address bus, so it can address 2^20 or 1,048,576 addresses. Each address represents a stored byte. To make it possible to read or write a word with one machine cycle, the memory for an 8086 is set up in to 2 banks of up to 524,288 bytes each. See figure.

8086 Memory Banks

One memory bank contains all the bytes which have even addresses such as 00000h, 00002h, and 00004h etc. the data lines of this bank is connected to the lower 8 bit data lines i.e. from D0 to D7 of 8086.

The other memory bank contains all bytes which have odd addresses such as 00001h, 00003h and 00005h etc. the data lines of this bank is connected to the upper 8 bit data lines i.e. from D8 to D15 of 8086.

Address line A0 is used for enabling the memory device in the lower bank. An addressed memory device in this bank will be enabled when A0 is low, as it will be for any even address.

Like address 00222h = 0000 0000 0010 0010 0010.

Address lines A1 to A19 are used to select the desired memory device in the bank and hence the desired byte in the device.

Address line A1 to A19 are also used to select the desired memory device in the upper bank and hence the desired byte. An additional part of enabling the upper bank memory device is handled by the BHE i.e. the bus high enable signal. This is multiplexed out from the 8086 at the same time as an address is sent out.  An external latch, strobbeed by the ALE signal, grabs the BHE signal and holds it stable for the rest of the machine cycle like it does for the address.

So now if we read a byte from or write a byte to an even address the A0 will be low BHE will be high enabling the lower bank and disabling the upper bank.

The main reason that the A0 and BHE signal work as they do is to prevent the writing of an unwanted signal.

BIOS Routine (in short)

• —  The ROM BIOS (Basic Input Output System) is part of the ROM based control system of an IBM PC or compatible that both defines the architecture of the computer to the software.
• —  provides the fundamental I/O services that are needed for the operation of the computer.
• —  The BIOS is actually a collection of procedures.
• —  Each procedure performs a specific function such as reading a character from the keyboard, writing characters to the screen, or reading information from disk.
• —  To call one of these procedures, load required parameters in specified registers and execute an INT N instruction. N in this case is the interrupt type which vectors to the desired type.

Interrupts in 8086

The meaning of ‘interrupts’ is to break the sequence of operation. While the cpu is executing a program, on ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).

After executing ISR , the control is transferred back again to the main program.

CPU checks for interrupts after every step.

Purpose of Interrupts

Interrupts are very helpful in data input output. CPU uses interrupts to communicate with I/o devices that provide data at a relatively low transfer rate.

Interrupts Types

They are divided into the group of 3.

Type 0 – Type 4: these perform fixed operation so are called dedicated interrupts.

Type 5 – type 31 are reserved for higher processors like 80386 etc etc.

Type 32 – type 255 are user defined interrupts. These can be hardware or software or can be acticvated by INTR line.

They are namely

Interrupt type	Description
Type 0 – divide error	8086 performs a complicated instruction like IDIV and DIV. so for connivance 8086 automatically does a divide by zero interrupt if the result of DIV and IDIV operation is too large to fit in the destination register or the divisor is 0. For type 0 interrupt, the 8086 pushes the flag register on the stack, resets IF and TF and pushes return address(CS and IP) on the stack. As this is automatic and cannot be disabled in any way, then you have to account for it whenever one uses IDIV and DIV. one way is to make sure results ever become larger than the register. Another way is to simply write an ISP which takes the desired action.
Type 1 – single step	When we tell a system to single step. It will execute 1 instruction then it will stop. We can then examine the contents of the registers and the memory. Basically it’s a debugging of our program. If we are statisfied we can tell the system to move on to the next instruction. In this system waits for our direction. The trap flag makes it easy to implement a single step feature. When trap flag is set =, it automatically does a type 1 interrupt. It pushes flag register on the stack, resets TF and IF and pushes CS and IP values for the next instruction on the stack.
Type 2 – non maskable	8086 automatically does a type 2 interrupt when it receives a low to high transition on its NMI pin. Again when acknowledged, it pushes flag register on the stack, resets TF and IF and pushes CS and IP values for the next instruction on the stack. The name nonmaskable given means that it cannot be disabled by any program instruction. If activated must be acknowledged by the processor. As this pin cannot be activated accidentally so we use it to signal the 8086 that some external condition needs to be taken care of.
Type 3 – breakpoint interrupt	This interrupt is produced by execution of INT 3 instruction. The main use is to implement a breakpoint function in a system. When we insert a breakpoint, the system executes all the instructions upto the inserted breakpoint then stops. CCh is the code for INT 3 instructions. We can use it to check our program execution in blocks. Or in simple system we can give control back to user. Or in a complicated system all execution summary can be displayed on a screen.
Type 4 – overflow	The overflow flag will be set if the signed result of an arithmetic operation on two signed numbers is too large to be represented in the destination register or the memory. There are 2 major ways to detect and respond to the overflow. One way is to put a jump instruction i.e jump on overflow right after the arithmetic operation so that it will jump to an error routine to show that overflow error has occurred. The second way of detecting is to put an interrupt on the overflow instruction, INTO immediately after arithmetic operation. If OF is not set it will work as NOP, but if its set it will give type 4 interrupt after it does INTO instruction.

Interrupt priority

Interrupt	Priority
DIVIDE ERROR, INTO, INT n	Highest
NMI
INTR
SINGLE STEP	Lowest