Harvard and Von-Neumann Architecture

In processor we need 2 kind of memory spaces program(to store code) and data.

Code – provides instructions to CPU.

Data – provides information to be processed to CPU.

The CPU uses buses to access the code ROM and data RAM memory spaces. The early computers used the same bus for accessing both code and data. Such an architecture is commonly known as von-neumann architecture. This means in von-neumann architecture there is only 1 bus for both data and program code. Meaning its going to be slow down the CPU’s processing speed as one has to wait for other to finish using the buses.

So to speed up the things, harvard architecture was introduced. In this we have separate buses for both program code and data memory. This means we need four sets of buses.

1)      To carry data in and out of CPU.

2)      To carry code into CPU.

3)      To carry address for accessing data.

4)      To carry address for accessing code.

Harvard architecture is usually implemented on microcontrollers.

Von Neumann is usually implemented on processors like x86 etc etc.

But why??

Implementing Harvard on microcontroller is damn easy as both RAM and ROM are on the same chip with distance of micron scale. But implementing it on x86 type PC its very expensive as in x86 both RAM and ROM are outside the CPU. Separate buses(wire traces) will make the motherboard very large and expensive.

Say for example a Pentium processor with 64 bit data bus and 32 bit address bus would require say about 100 wire traces in case of Von Neumann which will become 200 if Harvard architecture is used.

Harvard architecture will make it necessary that large number of pins comes out of processor itself. So for this reason we donot see Harvard architecture on our desktops and laptops.

The AVR uses Harvard architecture internally, but they still use von Neumann architecture if they need external ROM or RAM.

Von-Neumann and Harvard Architecture