8086 16bit microprocessor - the basics...

Basically 8086 has 2 units.

1)      BIU – Bus interface unit

2)      EU – Execution unit

8086 internal architecture. !!Sorry!! for the bad quality life without scanner is tough.

Execution Unit.

Contains control circuitry which directs internal operations.

A decoder in EU translates instructions fetched from memory into a series of action which EU carries out.

EU has 16 bit ALU which can add, subtract, AND,OR,XOR,increment,decrement,complement or shift binary numbers.

The figure below shows 8086 flag register format.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
U	U	U	U	OF	DF	IF	TF	SF	ZF	U	AF	U	PF	U	CF

Where,

U – Undefined

OF – Overflow flag

DF – String Direction flag

IF – Interrupt Enable flag

TF – Single Step Trap flag

SF – Sign flag

ZF – Zero flag

AF – Auxillary Carry flag

PF – Parity flag

CF – Carry flag

Flag	Use
Trap Flag – TF	Trap flag is used for single stepping through program
Interrupt Flag – IF	Interrupt flag is used to allow or prohibit the interruption of program.
Direction Flag – DF	Direction flag is used with string instructions.

General Purpose Registers.

8086 has 8 general purpose registers. Namely AH,AL,BH,BL,CH,CL,DH and DL.

All of these register are 8 bit in size.

Register AL is the accumulator.

Registers can be paired up to store 16 bit data. Pairing is as follows:

AH & AL as AX.

BH & BL as BX.

CH & CL as CX.

DH & DL as DX.

This set of general purpose register is very similar to earlier generation 8080 and 8085 microprocessors. Making program from previous processor highly transferrable to 8086 or 8088.

Bus Interface Unit.

Whats queue??

The first question that pops up in mind while observing the bus architecture is what is the queue? While EU is busy decoding an instruction or executing an instruction which does not require use of buses, the BIU fetches upto 6 instructions bytes for the following instructions. The BIU stores these prefecthed bytes in a FIFO register set called a queue.

When EU is ready for next instruction, it simply reads the instruction byte for instruction from queue in BIU. Except in the cases of JMP and CALL instructions, where queue needs to be dumped and then reloaded starting from the new address, this prefetch and queue scheme greatly increases processing speed. This process is called pipelining.

Segment Registers.

4 segment registers.

CS – Code Segment

SS – Stack Segment

ES – Extra Segment

DS – Data Segment

A segment register is used to hold the upper 16 bits of the starting address for each of the segments. The BIU always inserts zeros for the lowest 4 bits of the 20 bit starting address for a segment.

A stack is a section of memory set aside to store addresses and data while a subprogram executes. The stack segment register is used to hold upper 16 bits of the starting address for the program stack.

The extra segment register and data segment register are used to hold upper 16 bits of the starting address of 2 memory segments that are used for data.

IP – Instruction Pointer	The instruction pointer register holds the 16 bit address, or offset, of the next code byte within this code segment. The value contained is referred to as offset as this must be added to the segment base address in CS to produce the required 20 bit physical address sent out by the BIU.
SP – Stack Pointer Register	A stack is a section of the memory set aside to store address and data value while a subprogram is executing. The upper 16 bits of the starting address for stack segment are kept in stack segment register. The stack pointer register in EU holds 16 bit offset address from the start of the segment to the memory location where the most recent word was stored in the stack.
Pointer and Index registers in EU	EU also contains 16bit: BP – Base Pointer  SI – Source index DI – Destination index These 3 can be used for temporary storage just like general purpose register. Their main use is to hold the 16 bit offset of a data word in one of the segments.

Types of Buses Revisited.
Address Bus	The address bus consist of 16,20,24 and 32 parallel signal lines. On these lines CPU sends out the address of the memory location that is to be written to or read from. The number of address location accessed by CPU depends on number of address lines. If it has n address lines it can directly address 2^n address locations. For example 8086 can access 2^20 = 1,048,576 locations.
Data Bus	The data bus consist of 8,16 or 32 parallel signal lines. These are bi directional. Meaning CPU can both read and write in from memory or port from these lines. Any device connected on the data bus must have 3 state outputs so that its outputs can be disabled when it is not being used to put data on the bus.
Control Bus	The control bus consist of 4 to 10 parallel signal lines. The CPU sends out signals on the control bus to enable the outputs of addressed memory devices or port devices. Typical bus signals include: Memory Read Memory Write I/O Read I/O Write