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Sunday, February 26, 2012

Pin configuration 8086 and 8088

8086 Microprocessor
8088 Microprocessor
16 bit data bus
8 bit data bus
See Figure

See Figure

Has M/IO
Has IO/M

Pin Explanation

AD7-AD0 : address/data bus(multiplexed)
memory address or I/O port no : whenever ALE = 1
data : whenever ALE = 0
high-impedance state : during a hold acknowledge

AD15-AD8 : address/data bus(multiplexed)
memory address bits A15-A8 : whenever ALE = 1
data bits D15-D8 : whenever ALE = 0
high-impedance state : during a hold acknowledge

A19/S6-A16/S3 : address/status bus(multiplexed)
memory address A19-A16, status bits S6-S3
S6 : always remain a logic 0
S5 : indicate condition of IF flag bits
S4, S3 : show which segment is accessed during current bus cycle(Table 9-4)
S4, S3 : can used to address four separate 1M byte memory banks by decoding them as A21, A20

Function of Status bit S3 and S4
Extra Segment
Stack Segment
Code or no Segment
Data Segment

RD(bar) : read signal
data bus receive data from memory or I/O device :RD’=0

µ enter into wait states and remain idle : READY = 0

INTR : interrupt request
used to request a hardware interrupt
if INTR is held high when IF = 1 : µ enter interrupt acknowledge cycle(INTA’ become active) after current instruction has complete execution

TEST(bar)(BUSY(bar)) : tested by the WAIT instruction
WAIT instruction function as a NOP : if TEST’= 0
WAIT instruction wait for TEST’ to become 0:if TEST’=1

NMI : non-maskable interrupt
similar to INTR except that no check IF flag bit
if NMI is activated : use interrupt vector 2

µ : reset  if RESET held high for a minimum of four clock
CLK(CLOCK) : provide basic timing to µ
duty cycle of 33%

VCC(power supply) : +5.0V, ±10%

GND(Ground) : two pins labeled GND

MN/MX(bar) : select either minimum or maximum mode (HIGH for minimum mode)

BHE(bar)/S7 : bus high enable
status of S7 : always a logic 1
BHE=0 at least one byte of current transfer is to be made AD15-AD8 ( HIGHER ORDER BYTE)

IO/M(bar)(8088) or M/IO(bar)(8086) : select memory or I/O
address bus : whether memory or I/O port address

WR(bar) : write signal(high impedance state during hold ack).
strobe that indicate that output data to memory or I/O
during WR(bar)=0 : data bus contains valid data for M or I/O

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