Friday, March 1, 2013

Understandin ADC in AVR Microcontroller

To operate ADC in AVR microcontroller we need to understand certain register and their control word format.


ADMUX



ADMUX Register
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
REFS1 and REFS0 i.e. bit 7 and 6 are reference selection bits
These bits select the reference voltage for the ADC. Reference selection table is as shown below.
REFS1
REFS0
Vref
0
0
AREF Pin as reference voltage. Set externally using board potentiometer.
0
1
AVCC Pin as reference voltage. Voltage same as VCC i.e. 5 V.
1
0
Reserved. (Meaning not used)
1
1
Internal 2.56 V as reference Voltage. Remains fixed regardless of VCC Value.

Genral Value of ADMUX.
With internal 2.56 reference select, ADLAR High, and single ended input.
ADC0 – 0xE0
ADC1 – 0xE1
ADC2 – 0xE2
ADC3 – 0xE3
ADC4 – 0xE4
ADC5 – 0xE5
ADC6 – 0xE6
ADC7 – 0xE7

ADLAR i.e. bit 5. ADC left/right adjust results. By default its right adjust.
This bit dictates the result in ADCH:ADCL be left or right adjust. The AVRs have a 10-bit ADC meaning result is 10 bit long and cannot be stored into a single byte. So 2 registers are used to store that is ADCH:ADCL.See table below.

Justification
ADCH
ADCL
Left-Justified
ADLAR = 1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
UNUSED
Right-Justified
ADLAR = 0
UNUSED
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0




















MUX4 – MUX0 i.e. bit 4 to bit 0. These are analog channel and gain selection bits. These bits select the gain for the differential channels and also selects which combo of analog inputs are connected to ADC.
Is used to select single ended channels or differential channels. See table Below.

Single Ended Channels.
MUX4
MUX3
MUX2
MUX1
MUX0
Single Ended Output
0
0
0
0
0
ADC0
0
0
0
0
1
ADC1
0
0
0
1
0
ADC2
0
0
0
1
1
ADC3
0
0
1
0
0
ADC4
0
0
1
0
1
ADC5
0
0
1
1
0
ADC6
0
0
1
1
1
ADC7

See Image below for differential reference table.

Differential Input with Gain



ADCSRA


The ADCSRA register is the status and control register of ADC. Bits of this control or monitor the operation of ADC.
ADCSRA Register
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0

ADEN. Bit 7. ADC Enable. 1 will enable ADC. 0 will disable ADC.
ADSC. Bit 6. ADC Start Conversion. 1 to be setted to start each conversion.
ADATE. Bit 5. ADC Auto Trigger Enable. 1 Auto triggering of ADC is enable. 0 means Auto triggering off.
ADIF. Bit 4. ADC Interrupt Flag. This is set when conversion is completed and data registers are updated.
ADIE.Bit 3. ADC Interrupt Enable. Setting 1 enables ADC conversion complete interrupt. 0 disables it.
ADSP. Bit 2 to Bit 0. ADC Prescaler Select Bits. These bits determine the division between XTAL frequency and the input clock to ADC.

The Prescaler table is as shown below.
ADSP2
ADSP1
ADSP0
ADC Clock
0
0
0
Reserved
0
0
1
CLOCK/2
0
1
0
CLOCK/4
0
1
1
CLOCK/8
1
0
0
CLOCK/16
1
0
1
CLOCK/32
1
1
0
CLOCK/64
1
1
1
CLOCK/128

Important note. For the AVR the ADC requires input clock frequency less than 200khz for the maximum accuracy. See example below.
Example. For 16MHZ crystal.
ADSP 2:0 = 100 >>> 16MHZ/16 = 1MHZ which is not less than 200khz.
ADSP 2:0 = 101 >>> 16MHZ/32 = 500khz which is again not less than 200khz.
ADSP 2:0 = 110 >>> 16MHZ/64 = 250khz which is close but again not less than 200khz.
So the ADC input clock frequency for a 16MHZ crystal should have ADSP 2:0 = 111 which will give input clock – 16MHZ/128 = 125khz which is less than 200khz.