Assembly language program for 2 digit bcd to binary conversion

; GIVEN BCD NUMBER SAY 24
; IT IS STORED AS IT IS IN MEMORY
; EVEN THOUGH IT IS STORED AS HEXADECIMAL 24
; IT IS NOT HEXADECIMAL 24 IT IS BCD 24
; NOW FOR BINARY CONVERSION
; SEPARATE 24 TO 02 AND 04
; MULTIPLY 04 BY 0A 04 TIMES THEN ADD 02 TO GET BINARY NUMBER
; THIS IS IN SHORT A DECIMAL TO HEXADECIMAL CONVERSION




; MVI B, 24H ;
; MOV A, B ;
; ANI 0FH ;
; MOV C, A ;
; MOV A, B ;
; ANI F0H ;
; RRC ;
; RRC ;
; RRC ;
; RRC ;
; MOV D, A ;
; XRA A ;
; MVI E, 0AH ;


LOOP:


; ADD E ;
; DCR D ; MULTIPLY WITH 0A REGISTER D TIMES
; JNZ LOOP ;
; ADD C ;
; STA XXXXH ;
; HLT ; END OF PROGRAM

Absolute decoding VS Partial Decoding

ABSOLUTE DECODING


The decoding in which all available address line (16 lines in memory mapped and 8 lines in
peripheral mapping) are used for decoding to generate a unquie address is called absolute
decoding see fig.

ABSOLUTE DECODING

PARTIAL DECODING


The decoding in which all available address line(16 lines in memory mapping and 8 lines in
peripheral mapping) are not used for decoding resulting in multiple address for same port is
called partial decoding. see fig.

PARTIAL DECODING

IMPORTANT POINTS REGARDING INTERFACING

SOME IMPORTANT POINTS TO BE REMEMBERED WHILE DOING MAPPING
--> input and ouput port can have same address they can be differentiated by RD(bar) and
WR(bar) control signals.
--> In peripheral mapping it doesnot matter whether you use higher order address line or 
lower order address line. port address is duplicated on both segments of address 
lines.
--> To recongnize type of mapping just examine the control signal if its a MEMW/MEMR signal
then its a memory map if IOW/IOR signal its peripheral map.

Peripheral Mapped Input/Output

PERIPHERAL MAPPED I/O


--> has 8 bit device address
--> uses IOR(bar)/IOW(bar) as control signals for inout and output.
--> only IN and OUT instruction are available.
--> Data transfer occurs only between I/o and accumulator.
--> the I/O map is independent of memory map and 256 input and 256 ouput devices can be connected.
--> general execution speed of 10 T states.
--> less hardware is needed to decode 8 bit address line.
--> no arithmetic and logical operation are available.

PERIPHERAL MAPPED INPUT/OUTPUT

Memory Mapped Input/output

MEMORY MAPPED I/O


--> has 16 bit device address
--> MEMR(bar)/MEMW(bar) are control signals for input and output.
--> all memory related instruction like STA, LDA, LDAX etc are available.
--> Data transfer occurs between any register and I/O.
--> the memory map of 64K is shared between I/O and system memory.
--> general execution speed of 13 and 7 t states.
--> more hardware is required to decode 16 bit address.
--> arithmetic and logical operation can be directly performed with I/O data.

MEMORY MAPPED INPUT/OUTPUT

Timing Diagram for 7 T states instructions (F-R)

Timing Diagram for 7 T states instructions (F-R)

Timing Diagram for LDA and STA instruction.

Timing Diagram for LDA and STA instruction.

Timing Diagram for 12 States Instructions(S-W-W)

Timing Diagram 12 T states 

S=Fetch code with 6 t states.

W=Memory write

Timing Diagram for OUT instruction(F-R-IOW)

Out instruction

Timing Diagram for IN instruction(F-R-IOR)

Timing Diagram for 10 t states Fetch Memory Read Memory Read(F-R-R)

Timing Diagram for 7 States Instructions(F-W)

Timing Diagram for 7 T- States Fetch-write(F-W)

Timining Diagram of 4 T-States

4 Tstates has only Machine cycle that is Fetch(F)

4 T States

Some terms

INSTRUCTION CYCLE


Instruction cycle is defined as the time required to complete one instruction.The instruction cycle
consists of 1-6 machine cycle.


MACHINE CYCLE


Machine cycle is defined as the time required to complete one operation of accessing memory, I/O operation or
acknowlegding an external request. This cycle may consist of 3-6 T states.


T-STATE


T-state is defined as one subdivision of operation performed in one clock period. These internal subdivision are
in synchronisation with the system clock. And each T-state is precisely equal to one clock period.

SIGN FLAG

The flag is used to differentiate between signed and unsigned numbers. In a geven byte if D7 is 1, the number will be viewed as a negative number; if it is zero it will be viewed as a positive number.

ZERO FLAG

The zero flag is set when ALU operation leads to 0, and flag is reset if result is not zero.

AUXILLARY CARRY

In an arithmetic operation, when a carry is generated by digit D3 and passed to digit D4, AC flag is set. The flag is used internally for BCD operation and not available to programmer.

PARITY FLAG

After an arithmetic or logical operation if number of 1's in Accumulator is even it is set and if its odd it is reset.

CARRY FLAG

If an aritmetic operation results in a carry the flag is set otherwise it is reset. This also serve as a borrow flag for subtraction.