Instruction with 13,16 and 18 T-States

INSTRUCTION WITH 13 T STATES


STA 16bit address
LDA 16bit address


INSTRUCTION WITH 16 T STATES


XTHL (EXCHANGE HL WITH TOP OF STACK)
SHLD 16bit address(STORE HL DIRECT)
LHLD 16bit address


INSTRUCTION WITH 18 T STATES


CALL (UNCONDITIONAL)
CC,CNC,CP,CM,CPO,CPE,CZ,CNZ(CONDITION TRUE)

Instruction with 9,10 and 12 T-States

INSTRUCTIO WITH 9 T STATES


CC,CNC,CP,CM,CPO,CPE,CZ,CNZ
(CONDITION FALSE)


INSTRUCTION WITH 10 T STATES


DAD register pair(ADD REGISTER PAIR TO HL)
DCR M
IN 8-bit address
INR M
JMP (JUMP UNCONDITIONAL)
JC,JNC,JP,JM,JZ,JNZ,JPO,JPE(CONDITION TRUE)
LXI register pair/16bit immediate
MVI M, data
OUT 8bit address
POP register pair
RET (UNCONDITIONAL)


INSTRUCTION WITH 12 T STATES


RST 0, RST 1 ...... RST 7
RST (RESTART)
RC,RNC,RPO,RPE,RM,RP,RZ,RNZ(CONDITION TRUE)
PUSH register pair

Instruction with 7 T-States

ACI immediate
ADC M
ADD M
ADI immediate
ANA M
ANI immediate
CMP M (COMPARE WITH ACCUMULATOR)
CPI immediate
JC,JNC,JP,JM,JPE,JPO,JZ,JNZ(IN FALSE CONDITION)
LDAX register pair
MOV register, M
MOV M, register
MVI register, data
ORA M
ORI immediate
SBB M
SBI immediate
STAX register pair
SUB M
SUI immediate
XRA M
XRI immediate

Instruction with 6 T-States

DCX register pair
INX register pair
PCHL (LOAD PROGRAM COUNTER WITH HL CONTENTS)
SPHL (COPY HL TO STACK POINTER)
RC,RNC,RP,RM,RPE,RPO,RZ,RNZ
(FALSE RETURN CONDITION)

Instruction with 4 T-States

ADC register
ADD register
ANA register
CMA (COMPLEMENT ACCUMULATOR)
CMC (COMPLEMENT CARRY)
CMP register (COMPARE WITH ACCUMULATOR)
DAA (DECIMAL ADJUST ACCUMULATOR)
DCR register
DI (DISABLE INTERRUPT)
EI (ENABLE INTERRUPT)
INR register
MOV registerD, registerS
NOP (NO OPERATION)
ORA register
RAL (ROTATE ACCUMULATOR LEFT THROUGH CARRY)
RAR (ROTATE ACCUMULATOR RIGHT THROUGH CARRY)
RLC (ROTATE ACCUMULATOR LEFT)
RRC (ROTATE ACCUMULATOR RIGHT)
RIM (READ INTERRUPT MASK)
SBB register
SIM
STC (SET CARRY)
SUB register
XCHG (EXCHANGE H AND L WITH D AND E)
XRA register

8259 Operating Modes

MODES OF 8259


1) FULLY NESTED MODE


This is a general purpose mode where all IR's are arranged in highes to lowest.
IR0 highest and IR7 lowest.




2) AUTOMATIC ROTATION MODE


In this mode a device after being serviced receives the lowest priority.


3) SPECIFIC ROTATION MODE


In this user can select any IR for lowest priority thus fixing all priorities.

8259 Programmable interrupt controller

8259 Block diagram

READ/WRITE LOGIC


This is a typical read/write control logic. When A0 is low, the controller is selected 
to write a command. The chip select and A0 is used for determining port address.


CONTROL LOGIC


This has 2 pins INT(interrupt) and INTA(bar)(interrupt acknowledge) as input.
The INT is connected to MPU. Whereas the INTA(bar) is interrupt acknowledege 
from MPU.


INTERRUPT REGISTER AND PRIORITY RESOLVER


The interrupt request register(IRR) has 8 input lines. IR0 - IR7 for interrupts.
The request are stored in the register. 
The In service register(ISR) stores all levels that are currently being serviced. 
The interrupt mask register(IMR) stores the masking bits of interrupts lines to
be masked.
The priority resolver(PR) examines these registers and determines whether to send
INT to MPU or not.


CASCADED BUFFER/COMPARATOR


This is used to expand number of interrupts levels by cascading 2 or more 8259's.

Write a subroutine in Assembly language to generate pulse every 50uS from counter 0 of 8254

; ASSUMPTION 8254 IS CONNECTED AT PORT 80H
; MEANING
; D7 D6 D5 D4 D3 D2 D1 D0
; 1 0 0 0 0 0 0 0
; HERE D1 -A1
; AND  D0 -A0
; WHERE A1 A0 ARE SELECTION LINES FOR COUNTER 0,1,2, AND CONTROL REGISTER
; SO 80H REFERS TO COUNTER 0
; 81H REFERS TO COUNTER 1
; 82H REFERS TO COUNTER 2
; 83H REFERS TO CONTROL REGISTER
; FOR SELECTION OF COUNTER 0


; SELECET LOAD COUNT MODE SELECTION 0,1,2 BINARY
; COUNTER 8-BIT 3,4, OR 5 COUNT
; D7 D6 D5 D4 D3 D2 D1 D0
; 0 0 0 1 0 1 0 0 FOR COUNTER 0
; 0 1 0 1 0 1 0 0 FOR COUNTER 1
; 1 0 0 1 0 1 0 0 FOR COUNTER 2
; WHICH GIVES US
; 14H
; 54H
; 94H
; 
;
; ASSUME 2MHZ FREQUENCY OF MPU
; THEREFORE CLOCK CYCLE = .5us
; NOW COUNT HERE TAKEN IS 8 BIT WHY??
; BECAUSE 
; COUNT = 50us/.5us = 100 = 64H
; PROGRAM GOES AS SHOWN


MVI A, 14H ; FOR COUNTER 0
OUT 83H ; WRITE TO CONTROL REGISTER
MVI A, 64H ; AS COUNT IS 8-BIT
OUT 80H ; LOAD COUNTER 0 WITH GIVEN
RET ; AS THIS IS A SUBROUTINE

8254 Operating Modes

8254 MODES

MODE 0: INTERRUPT ON TERMINAL COUNT

In this mode OUT is low. Once a count is loaded the counter is decremented after every cycle,

and when count reaches zero, the OUT goes high. 

This can be used as an interrupt. The OUT remains high until a new count or command word is 

loaded.

MODE 1: HARDWARE RETRIGGERABLE ONE SHOT

In this mode OUT is intially high. When gate is triggered, the OUT goes low, and at the end of

count it goes high again, thus generating a one shot pulse.

MODE 2: RATE GENERATOR

The mode is used to generate a pulse equal to given clock period at a given interval.

When a count is loaded, the OUT stays high until count reaches 1 and then OUT goes low

for 1 clock period then gets reloaded automatically and this is how pulse gets generated 

continuously.

MODE 3: SQUARE WAVE GENERATOR

In this a continuous square wave with period equal to count is generated. 

The frequency of square wave = frequency of clock divide by count.

if count (N) is odd pulse stay high for (N + 1)/2 and low for (N - 1)/2.

MODE 4: SOFTWARE TRIGGERED STROBE

In this mode OUT is initially high, it goes low for one clock period at the end of count.

The count must be reloaded for subsequent outputs.

MODE 5: HARDWARE TRIGGERED STROBE

Same as MODE4 except that it is triggered by rising pulse at gate.

8254/8253 Programmable interval timer

SHORT DESCRIPTION


The 8254 includes 3 identical 16-bit counter that can operate independently in any one of the 6 modes.
This includes a Status read back Command that can latch the count and status of counter.

8254 Block Diagram

Each counter has 2 input signals CLK and GATE and one output signal OUT.

DATA BUS BUFFER

This tri state 8-bit bidirectional buffer is connected to data bus of MPU.

CONTROL LOGIC

This section has 5 signals RD(bar)(Read) WR(bar)(Write) CS(bar)(Chip select) and address line

A0 and A1.

In peripheral I/O mode 

RD(bar) - IOR(bar)

WR(bar) - IOW(bar)

In Memory mapped mode

RD(bar) - MEMR(bar)

WR(bar) - MEMW(bar)

A0 and A1 decoded address

A0 A1 Selection

0 0 Counter 0 

0 1 Counter 1

1 0 Counter 2

1 1 Control Register

8279 Programmable Keyboard/display interface

Short Description
This is a hardware approach to interface a matrix keyboard and a multiplexed display.
The display can be set as a right entry or a left entry.

8279 Block Diagram

KEYBOARD SECTION


This sectio has 8 lines. RL0 - RL7. Plus 2 additional lines. Shift and CNTL/STB. The keys are automatically debounced and keyboard can operate in two modes:
>>two key lockout mode or
>>N-key rollover.
In two key lockout mode if 2 keys are pressed simultaneously only firstkey is recongnized.
In N key rollover mode, simultaneous keys are recongnized and stored in internal buffer: it can also
be set up so that no key is recongnized until only one key is remained pressed.


This has a FIFO RAM.
The status logic keeps track of number of entries and provides IRQ(interrupt request) signal when
FIFO is empty.


DISPLAY SECTION


This section has 8 output lines divided into 2 groups of 4. A0 - A3 and B0 - B3.
These lines can be used in both ways 8 lines or 2 sets of 4 lines.
The display can be blanked using BD line. The section has 16x8 display RAM.


SCAN SECTION


This section has scan counter and 4 scan lines. SL0 - SL3. These 4 scan lines can be 
decoded using a 4 - 16 decoder to generate 16 lines for scanning.
These 16 lines can be connected to rows of a matrix keyboard and digit driveers of multiplexed
display.


MPU INBTERFACE SECTION


This section has 8 bi directional lines. DB0 - DB7. 1 interrupt request line(IRQ). 
6 lines for interfacing including buffer address lines A0.


When A0 is high - signals are interpreted as control word or status.
When A0 is low - signal is interpreted as data.
IRQ goes high whenever data is ready to be loaded into MPU.


QUESTIONS FOR ABOVE CONTEXT
Q) List major components of 8279 and explain their function
Q) Explain block diagram of 8279.

8259 Control word format

8255 Control word format

8254 Control word format

Nyquist Plots (a short theory)

Nyquist Plots are a way of showing frequency responses of linear systems.  There are several ways of displaying frequency response data, including Bode' plots and Nyquist plots.

  Bode' plots use frequency as the horizontal axis and use two separate plots to display amplitude and phase of the frequency response. 

  Nyquist plots display both amplitude and phase angle on a single plot, using frequency as a parameter in the plot. 

  Nyquist plots have properties that allow you to see whether a system is stable or unstable.  It will take some mathematical development to see that, but it's the most useful property of Nyquist plots.

Nyquist Plots were invented by Nyquist - who worked at Bell Laboratories, the premiere technical organization in the U.S. at the time.  He was interested in designing telephone amplifiers to be placed in ocean-floor cables.  In those days, between the first and second world wars, undersea cables were the only reliable means of intercontinental communication.

Undersea telephone cables needed to be reliable, and to have a constant gain that did not change as the amplifier aged.  In those days, electronic amplifiers were constructed with tubes, and tubes had gains that could change dramatically as they aged.

The solution to the aging problem was to design feedback amplifiers.  However, those amplifiers could become unstable.  One morning - going to work on the Staten Island ferry, before the Verrazano Narrows bridge - Nyquist had an inspiration, and wrote his work, literally, on the back of an envelope as he rode. 

A Nyquist plot is a polar plot of the frequency response function of a linear system.

That means a Nyquist plot is a plot of the transfer function, G(s) with s = jw.  That means you want to plot G(jw).


G(jw) is a complex number for any angular frequency, w, so the plot is a plot of complex numbers.


The complex number, G(jw), depends upon frequency, so frequency will be a parameter if you plot the imaginary part of G(jw) against the real part of G(jw).

An example of a Nyquist plot will illustrate what a Nyquist plot is.

We will take a very simple system:  G(s) = 1/(s+1).
If we substitute s = jw, we get G(jw) = 1/(jw + 1).
Now, compute the real and imaginary parts of G(jw) by converting the denominator to a real number.

or:

Now, the real part of the frequency response function is:

Real(G(jw)) = 1/(1+w²)

And, the imaginary part is:

Imag(G(jw)) = jw/(1+w²)

- or you may prefer that we express this as:

 Imag(G(jw)) = w/(1+w²) - leaving off the j.

        Now, to generate a Nyquist plot we would need to plot the imaginary part on the vertical axis of a plot, and the real part on the horizontal axis.  Here is a video of that operation.

        The point at which the phase angle becomes -45^o is important.  You can read the frequency from the clip.  Determine the frequency on the clip at which the phase is closest to -45^o.

        Now, since the transfer function, G(s), is 1/(s + 1) for this example, we can determine what should have been the answer, not just the closest frame on the video.  Let's determine the frequency at which the phase angle is -45^o.

• The frequency response function is G(jw) = 1/(jw + 1).
• The phase angle is -45^o when the angle of the denominator is +45^o.
• The angle of the denominator is tan^-1(w).
• Solving for the frequency, w, we get w = 1.0.
• If w = 1.0, then f =  w/2p = .159 Hz.

        The video of the Nyquist plot isn't really a true Nyquist plot.  A true Nyquist plot shows the frequency response function for all frequencies, not just a single -albeit moving - point.  So, let's take a look at the Nyquist plot for G(s) = 1/(s + 1).  Here it is!

Now, let us look at some interesting points in this Nyquist plot.

• The low frequency portion of the plot is near +1.  That makes sense since the DC gain is 1 for G(s) = 1/(s + 1).
• The high frequency portion of the plot is near the origin in the G(jw) plane.  That makes sense because the magnitude becomes small as frequency gets large.
• The high frequency portion of  the plot approaches the origin at an angle of -90^o.  That makes sense because the phase approaches -90^o as the frequency gets large.

        What's wrong with all of this?  Is there something else we should note?

• The frequency is a parameter of the plot, and unless we do something, there will be no indication of what frequency corresponds to a particular point on the plot.
• We can indicate direction of increase of frequency with small arrows along the plot.  Using those arrows is  more- or-less standard practice.
• We will always assume that the plot starts at zero frequency and frequency goes to infinity.

        At this point, you have seen one Nyquist plot.  We need to consider a few more points about Nyquist plots.

• You need to learn what Nyquist plots look like for different systems, including second order systems, higher order systems, systems with resonant peaks and systems with poles and zeroes at the origin of the s-plane.
• You need to learn how you can generate Nyquist plots.

High Frequency Asymptotes        There are other points you need to note about Nyquist plots. Let's start by considering how a Nyquist plot is affected when the system has a higher order.

• First, consider a more general transfer function.  Most transfer functions are a ratio of polynomials in s.  Here is a typical example - shown in factored form.
• This system has m zeroes.
• This system has n poles.

• It is almost always true that the denominator is of higher order than the numerator so,

n  > m, i.e.#Poles > # Zeroes

• Although, on occasion we have:

n = m, i.e.#Poles = # Zeroes

• The system has n poles and m zeroes.
• We remind you that a stable system will have all of the poles in the left half of the s-plane, so all of the p's will be negative in G(s).  Also, zeroes will usually be in the left half of the s-plane, but it's possible that is not the case.

        Now, let us assume - at least for the moment - that:

• The transfer function has no poles at s = 0.  We normally say that the system has no poles at the origin.
• We are going to examine the behavior of the Nyquist plot for large frequencies.
• Let s = jw in the transfer function to obtain:

Then, if we let the frequency become very large.  In the limit, each jw term will "overpower" the corresponding z or p term in G(jw) and we will have:G(jw) ~= 1/(jw^n-m)        The angle of this limiting form is what we are interested in now, and the angle is determined by the j-term.

• The angle is determined by the power of j.  You get -90^o for every j.
• For example, if n = 4, and m = 1, then n - m = 3, and for high frequencies the Nyquist plot would have an angle of -270^o.

        Here are some examples.  For each example, think about the asymptotes, then click on the hot word or the Nyquist plot to show the high frequency asymptote when you have determined what the angle should be.

• A first order system, G(s) = 1/(s + 1)
• Click on the button to see the high frequency asymptote.
• The high frequency asymptote is at -90^o which is where it should be for a system with one more pole than zero.

• A second order system, G(s) = 1/(s + 1)²
• Click on the button to see the high frequency asymptote.
The high frequency asymptote is at -180^o which is where it should be for a system with two more poles than zeroes.

• A third order system, G(s) = 1/(s + 1)³
• Click on the button to see the high frequency asymptote.
The high frequency asymptote is at -270^o which is where it should be for a system with three more poles than zeroes.

        The example third order system is not easily seen.  However, you can change the scale for that system, and see things more clearly.  If you have a problem seeing the asymptote you may want to change scales when you have to do this kind of analysis.

Write assembly language program to enable all interrupts

EI
MVI A, 08H ; LOAD BIT PATTERN TO ENABLE 7.5, 6.5 AND 5.5
SIM ;
; REMEBER 0 ENABLES THE INTERRUPTS WHEREAS
; 1 MASKS THE INTERRUPTS
; SO THE IMMEDIATE VALUE OF A DEPENDS ON OUR USE

8085 Interrupts theory and instruction(short)

INTERRUPTS
The interrupt I/O is a process of data transfer whereby an external device or a peripheral can inform a proccessor that it is ready for communication and it request attention.
The interrupt is not an order to the processor to do an action its a request to listen to the action and do if feasible.
The 8085 has 4 Maskable and 1 Non Maskable interrupt.
Interrupts           Call Location
1) Trap -------->    Pre Fixed (0024h)
2) RST 7.5 --------> Pre Fixed (003Ch)
3) RST 6.5 --------> Pre Fixed (0034h)
4) RST 5.5 --------> Pre Fixed (002Ch)
5) INTR -------->    Provided by device


Number 1,2,3,4,5 shows priority.


The first four are vectored interrupts meaning when activated jumps to specified location.


The last one is non vectored meaning the call location needed to be provided by the device.


The microprocessor can ignore or delay a maskable interrupt request if it is performing some critical task; however it has to respond to non maskable interrupt request immediately.


Instruction used in interrupts.
DI - Disable interrupt
-->> Bytes - 1
-->> M-cycles - 1
-->> T-states - 4
-->> Description - The interrupt enable flip flop is reset and all the interrupts except the TRAP are disabled.
-->> Use - This is commonly used when the execution of a code sequence cannot be interrupted. For example in critical time delays, this instruction is used at the beggining of the code and
interrupts are enabled at the end of the code.


EI - Enable Interrupt
-->> Byte - 1
-->> M-cycles - 1
-->> T-states - 4
-->> Description - The interrupt enable flip flop is set and all interrupts are enabled.
-->> Use - After a system reset or the acknowledgement of an interrupt, the interrupt Enable flip flop is reset, thus disabling the interrupts. This instruction is necessary to re enable the instruction.


TRAP
TRAP, a non mask able interrupt known as NML.
It has highest priority among interrupt signals, need not be enabled or disabled.
It is level and edge sensitive trigger, meaning that input should go HIGH and stay HIGH to be acknowledged.
It cannot be acknowledged again until it makes a transition from HIGH to LOW to HIGH.
TRAP is generally used for critical events like power failure and emergency shutdown.

SIM
Set Interrupt Mask.

Format of SIM in Accumulator

RIM
Read Interrupt Mask

Format of RIM in Accumulator

Interrupt Table in Short

8085 Addressing Modes

Addressing Modes


The microprocessor has different ways of specifying the data for the instruction. These are called “addressing modes”.


The 8085 has Five addressing modes:


1)  Implied Addressing mode: In this type of addressing mode, No operand (register or data) is specified in the instruction. The operand is inherent to the instruction. 
    
Example:   CMA (Complement Accumulator) , SIM , RIM etc 
  
2)  Immediate Addressing Mode: In this type of addressing mode, immediate data byte is provided with the instruction. 


Example: MVI A  32H; 
         MVI B  AAH; 
etc. 


3)  Direct Addressing Mode: In this type of addressing mode, the 16bit memory address is directly provided with the instruction. 


Example:   LDA C500H ;
etc 


4)  Indirect Addressing Mode: In this type of addressing mode, the 16bit memory address is indirectly provided with the instruction using a register pair


Example:   LDAX  D;   
(Load the accumulator with the contents of the memory location whose address is stored in the register pair DE)

5)  Register Addressing mode:   This type of addressing mode specifies register or register pair that contains data. 


Example:   ADD B;  
           MOV B, A;